When I interned at IBM and this was a big deal. IBM was really invested on being "vertically" integrated "from sand to software" as they would say. One wonders what another run at this concept would be like given advances in semiconductor manufacture.
I have often wondered if a chip fab that could make 1,000 chips of a given type economically (which is to say using your custom chip in your system was less expensive than adopting an off the shelf chip) would be a thing. The whole 'tiny tapeout' thing would be a lot more interesting too.
Given that there are only three companies in the world even capable of competing on the sand side, I'd say that window of opportunity is increasingly shrinking.
Jim Keller is working on a small fab design that is intended to make small runs economic. Atomic Semi. Hasn't yielded anything yet, but they only started in 2023.
It's not the wafer cost. The masks (the "negatives" for the lithography) are the problem. A mask set (you need multiple exposures for one device) for a modern EUV node costs 20-30m$. That's the limiting factor. You can't get cheaper than that.
As a sibling comment notes, multi-product wafers are a theoretical answer. However, since you have process corners (manufacturing defects aren't uniformly distributed on the wafer), it is unfeasible for anything but the cheapest parts.
The real next moonshot in the foundry business would be to lower the respin costs, i.e., the amount of money it costs when your fabbed first silicon doesn't yield or validate functionally in the way you had expected/planned.
If I were the US government (or any other), I'd focus on that. Subsidize the respin cost to zero in the short-term, given certain prerequisites for start-ups, and push an all-out Manhatten project RnD effort to lower the respin cost in the long run.
Multibeam corporation is making “maskless” lithography tools:
I get that for state of the art fabs. Those optimize for long runs on big wafers. My question though is can you find a solution at a different node which favors cost/turnaround at the expense of not scaling?
For example, could one make a 200nm node with conventional UV masks and a limit of say 10 layers? Non mask lithography options? Or as in the article 'sub' masks where you step a single die image across the wafer?
Multi product wafers are a thing, especially on older nodes. It’s accessible to hobbyists
Node size and price / sq mm? The last time I looked at what it would cost to have a partial wafer it was > $25,000 (of which slightly more than half was NRE charges) but would love to find something "hobbyist accessible." !
My understanding is that a chip design for one fab isn’t portable to another.
How does can hobbyist design be just be slapped onto a wafer (with others’ designs) and call it a day?
Indeed, you develop using a fab-specific PDK. But if you share a (Tower Semi, for instance) PDK, your device can have shuttle wafers with multiple designs from different companies. This is done for old nodes and low-volume or RnD parts.