What does 'layer' mean in this context? I'm only familiar with planar style logic process nodes which have maybe up to 20 layers (and way more lithography steps to manufacture those layers), but I am completely ignorant of how the term is used for a flash process node.
How many layers are needed for each physical cell? Is it 1,2, or a lot more? Is this effectively 321 physical TLC cells stacked vertically and some planar style logic at the bottom of the stack.
Also, where do multiple pieces of silicon factor into this - I assume we might be up to 16 silicon dies deep with through-silicon-vias, which would mean a cross section of a package could actually have 5000 layers - that sounds crazy!
Probably done with 3 separate litho/etch layers, where they etch and process in groups of 110 or so.
Each of those layers can have a cell, so if you have a tlc device at a 100nm pitch, you have a density of 321*3/(1e-4)^2 bits/mm, or about 1e11bits/mm2.
Fun reference: atomic density is 1atom/.5nm, so 1/5e-7^2, or 4e12/mm2 ish.
Not too far away.
Amazing, I had no idea how far things had diverged between logic and flash since the move to 3D.
https://borecraft.com/files/Comparison_Current_NAND.pdf (from 2019) has some of the cross-sections I was looking for - and that only goes up to 96 layers!